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Espressif Systems /ESP32-C6 /SPI0 /SPI_MEM_INT_RAW

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Interpret as SPI_MEM_INT_RAW

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_SLV_ST_END_INT_RAW)SPI_MEM_SLV_ST_END_INT_RAW 0 (SPI_MEM_MST_ST_END_INT_RAW)SPI_MEM_MST_ST_END_INT_RAW 0 (SPI_MEM_ECC_ERR_INT_RAW)SPI_MEM_ECC_ERR_INT_RAW 0 (SPI_MEM_PMS_REJECT_INT_RAW)SPI_MEM_PMS_REJECT_INT_RAW 0 (SPI_MEM_AXI_RADDR_ERR_INT_RAW)SPI_MEM_AXI_RADDR_ERR_INT_RAW 0 (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW)SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW 0 (SPI_MEM_AXI_WADDR_ERR_INT_RAW)SPI_MEM_AXI_WADDR_ERR_INT_RAW

Description

SPI0 interrupt raw register

Fields

SPI_MEM_SLV_ST_END_INT_RAW

The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
SPI_MEM_MST_ST_END_INT_RAW

The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.
SPI_MEM_ECC_ERR_INT_RAW

The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.
SPI_MEM_PMS_REJECT_INT_RAW

The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.
SPI_MEM_AXI_RADDR_ERR_INT_RAW

The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.
SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW

The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.
SPI_MEM_AXI_WADDR_ERR_INT_RAW

The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data